It has facility to demultiplexed the binary data stream and recover
of the original waveform, using digital to analog conversion
Input channels : 2 numbers time division multiplexed
code (de-modulated)
Receiver clock : Generated by phase lock loop (Fast
mode)
Parity check facility : Even, odd, hamming, No-parity
Error Detection : Single bit error detection on LED,
when even or odd parity mode is selected
Correction facility : Single bit error detection &
correction, when hamming parity code is selected
Low pass filter cut-off points : 3.4KHz
LED Display : At every functional block for examination
of Digital data and control signal
Interconnection : 2mm banana socket
Power Supply : +5V, +/-12V
LIST OF EXPERIMENT
